Multimodal Data Switch

ABSTRACT

A transit memory assembly of a rotator-based switching node is logically partitioned into two sections, one operated as a common-memory switch fabric and the other as a time-shared space-switch fabric. The composition of data received at input ports of the switching node determines adaptive capacity division between the two sections. Based on an indication of traffic type, a controller of at least one input port selects one of the two sections. The space-switch section enables scalability to a high transport capacity while the common-memory section enables scalability to a high processing throughput. 
     The switching node includes rotators and a bank of transit-memory devices that facilitate the incorporation of any mixture of periodic, aperiodic, contention-free exclusive-access, concurrent-access, and multicast switching.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of U.S. patent application Ser. No.11/002,398, entitled MULTIMODAL DATA SWITCH, filed Dec. 2, 2004, whichis incorporated by reference.

FIELD OF THE INVENTION

The present invention relates to multi-service switching nodes and, moreparticularly, to an architecture and a control mechanism of a multimodalelectronic switch.

BACKGROUND

The conventional common-memory data switch has the advantages of extremesimplicity, high-performance, ease of multicasting, and ease ofscheduling in comparison with other data switches. In a common-memoryswitch, each input port has exclusive access to a common memory over adesignated interval in a time frame and, similarly, each output port hasexclusive access to the common memory during a designated interval inthe time frame. The total capacity, in bits per second, of the commonmemory switch is therefore determined by the width and the access time(read and write) of the common memory. In a symmetrical switch, thetotal capacity is the capacity of the input side or the output side ofthe switch. To realize a capacity of 640 gigabits per second, forexample, using a memory of access time (read and write) of 20nanoseconds, the memory width would be 12.800 kilobits (1.6 Kilobytes).When an input port accesses the common memory, it writes a data blockdestined to at least one output port. In order to fully use the capacityof the switch, the size of the data block should be equal to the widthof the common memory. The time required to form, at an input port, adata block directed to an output port can be excessive when the flowrate of a data stream from an input port to an output port is relativelylow. A requirement to keep the data-block formation below an acceptablevalue may limit the scalability of the common-memory switch. Thus, whilescheduling and control simplicity of a common-memory switch wouldfacilitate capacity growth, the scalability of the switch is determinedprimarily by the switching fabric limitation.

Well-known conventional switch structures based on time-shared spaceswitches would allow the construction of a switching fabric of highcapacity. However, the scalability of such structures may be limited byscheduling and control complexity.

The main advantage of the common-memory switch is the absence ofinternal contention which facilitates scheduling and improvesperformance. The main advantage of the space-switch is the ease ofexpansion to high fabric capacities. The main limitation of thecommon-memory switch is fabric scalability in terms of the number ofports. The main limitation of the time-shared space switch is thescheduler scalability. A common-memory fabric is suitable for datastreams of high flow rates while a time-shared-space-switch fabric issuitable for data streams of relatively low flow rates. In order toprovide a data network serving data streams of widely varying flow ratesand different service requirements, a switching-node structure thatcombines the advantages, and circumvents the limitations, of thecommon-memory structure and the space-switch-based structure is needed.

SUMMARY

A switching node of a homogeneous fabric functions as a combinedcommon-memory switch and time-shared space switch serving data streamsof widely-varying flow rates. The combined switch serves aperiodicvariable-rate data and periodic data in both fine and coarsegranularities and in both unicast and multicast modes.

In accordance with an aspect of the present invention, there is provideda switch comprising: a plurality of input ports; a plurality of outputports; and a plurality of transit-memory devices each transit-memorydevice cyclically connecting to each of the input ports and output portsduring a predefined time-slotted frame. Each transit-memory device islogically partitioned into a first group of primary memory divisionseach for holding a data segment from any of the input ports destined toany of the output ports; and a second group of secondary memorydivisions having a one-to-one correspondence to the output ports. Theprimary memory divisions are arranged into memory blocks each memoryblock including one primary memory division from each transit-memorydevice, and each memory block is allocable to hold a data block thatincludes at least one data segment written by a single input port anddestined to at least one output port.

The switch further comprises: a plurality of transit-memory controllerseach transit-memory controller associated with each of thetransit-memory devices; and a master controller communicatively coupledto each of the input ports and each of the transit-memory controllers.

In accordance with another aspect of the present invention, there isprovided a switch comprising: a plurality of input ports for receivinginput data and organizing the input data into data segments; a pluralityof output ports for transmitting output data; a plurality of transitmemory devices; a plurality of transit-memory controllers, eachtransit-memory controller associated with a specific transit memorydevice; an input rotator operable to cyclically connect each input portto each transit memory device; an output rotator operable to cyclicallyconnect each transit memory device to each output port; and a mastercontroller communicatively coupled to each of the input ports and eachof the transit-memory controllers.

Each transit-memory controller is operable to allocate a dedicatedmemory division in the specific transit memory device to each outputport for receiving from any input port a data segment destined to theeach output port, thereby realizing concurrent-access switching. Eachtransit-memory controller is also operable to reserve a prescribednumber of floating memory divisions in the specific transit memorydevice, each floating memory division for receiving from any input porta data segment destined to at least one output port.

The master controller is operable to allocate at least one array offloating data divisions, each array including one floating memorydivision from each transit memory device, for transferring a data blockfrom a selected input port to at least one output port, the data blockincluding a number of data segments not exceeding the number of thetransit memory devices, thereby realizing exclusive-access switching.

In accordance with a further aspect of the present invention, there isprovided a method of scheduling transfer of time-slotted signals from aplurality of input ports to a plurality of output ports through a numberof transit memories. The method comprises steps of: associating, duringeach time slot in a time-slotted frame, each input port with acorresponding one of the transit memories; creating a first matrixhaving a number of rows equal to the number of transit memories and anumber of columns equal to the number of input ports, with each entry inthe first matrix indicating a corresponding input-port occupancy state;creating a second matrix having a number of rows equal to the number oftransit memories and a number of columns equal to the number of outputports with each entry in the second matrix indicating a correspondingoutput-port occupancy state; and matching entries in the first matrixand the second matrix in response to a request to transfer signals overa specified number of time slots from a specified input port to aspecified output port within the time-slotted frame.

Other aspects and features of the present invention will become apparentto those of ordinary skill in the art upon review of the followingdescription of specific embodiments of the invention in conjunction withthe accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

In the figures which illustrate example embodiments of this invention:

FIG. 1 illustrates a prior-art common-memory switch;

FIG. 2 illustrates data organization into time-slotted frames switchedin the common-memory switch of FIG. 1;

FIG. 3 illustrates a prior-art data switch using a space switch, inputbuffers, and output buffers;

FIG. 4 illustrates delay limitations of a common-memory switch;

FIG. 5 further illustrates the dependence of data-block formation delayat an input port in a common-memory switch on data flow rate, for usewith an embodiment of the present invention;

FIG. 6 illustrates the dependence of an upper bound of the number ofinput ports on data-stream flow rates in a common-memory switch, for usewith an embodiment of the present invention;

FIG. 7 illustrates an exemplary flow-rate distribution in a datanetwork, for use with an embodiment of the present invention;

FIG. 8 illustrates a prior art rotator-based switching node including aninput rotator, an output rotator, and a bank of transit-memory devices;

FIG. 9 illustrates a switching node comprising an input rotator, anoutput rotator, a bank of transit-memory devices, a transit-memorycontroller associated with each transit memory device, and a mastercontroller in communication with the input ports and the transit-memorycontrollers, in accordance with an embodiment of the present invention;

FIG. 10 illustrates the organization of transit memory in the dataswitch of FIG. 9, where the switch is adapted to perform bothconcurrent-access and exclusive-access switching, in accordance with anembodiment of the present invention;

FIG. 11 illustrates the use of the switch of FIG. 9 as anexclusive-access switch for switching data blocks each comprising anumber of data segments, with data blocks organized in thetransit-memory devices as an interleaved linked list with spatialalignment of the data blocks, in accordance with an embodiment of thepresent invention;

FIG. 12 illustrates the use of the switch of FIG. 9 as anexclusive-access switch for switching data blocks each comprising anumber of data segments, with data blocks organized in thetransit-memory devices as an interleaved linked list with temporalalignment of the data blocks, in accordance with an embodiment of thepresent invention;

FIG. 13 illustrates data organization in the transit memory devices in acombined exclusive-access and concurrent-access switch with spatialalignment of data blocks, according to an embodiment of the presentinvention;

FIG. 14 illustrates the data organization in the transit memory devicesin a combined exclusive-access and concurrent-access switch withtemporal alignment of data blocks, according to an embodiment of thepresent invention;

FIG. 15 illustrates the use of the switch of FIG. 9 as atime-division-multiplexing (TDM) switch with an arbitrary number of datasegments per time frame, in accordance with an embodiment of the presentinvention;

FIG. 16 illustrates the transit-memory access pattern in the switch ofFIG. 15 where the number of time slots per TDM frame is smaller than thenumber of transit-memory devices;

FIG. 17 illustrates the transit-memory access pattern in the switch ofFIG. 15 where the number of time slots per TDM frame is equal to thenumber of transit-memory devices;

FIG. 18 illustrates the transit-memory access pattern in the switch ofFIG. 15 where the number of time slots per TDM frame is larger than thenumber of transit-memory devices;

FIG. 19 illustrates data structures used by a controller forexclusive-access multicasting in a multimodal data switch, in accordancewith an embodiment of the present invention; and

FIG. 20 illustrates concurrent-access multicasting in a multimodal dataswitch, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION Exclusive-Access Switch

A communications switch comprises a plurality of input ports and aplurality of output ports interconnected by a switching fabric. Anyinput port may connect to any output port, or to several output ports,and the connectivity pattern may change with time. The switching fabricmay comprise memory devices, memoryless space switches, or a combinationof memory devices and memoryless space switches.

In a switch structure known as a common-memory switch, the switch fabricincludes a bank of random-access memory devices, together forming a widememory, also called a common memory. In the common-memory switch, eachinput port has an exclusive write access to the wide memory during adesignated interval of time within an arbitrarily specified time frame.Likewise, each output port has an exclusive read-access to the widememory during a designated interval of time within the time frame. Atany instant of time, only one input port or only one output port mayhave access to the wide memory. Thus, the wide-memory access iscontention free. During a common-memory access cycle, each of aplurality of input ports accesses the common memory to write a datasegment and each of a plurality of output ports accesses the commonmemory to read a data segment. The duration of the common-memory cycleis herein called a common-memory period. While an input port is waitingfor its designated write-access interval, it accumulates the data itreceives from subtending data sources, or from another switch, andarranges the data in a wide data block which is written in the widememory during the designated access interval of the input port.Likewise, while an output port is waiting to read a data block from thewide memory, it transmits a previous data block received from thecommon-memory cycle to subtending data sinks or to another switch. Adata block may contain packets belonging to several data sinks.

The maximum size of the data block transferred from an input port to thewide memory is determined as the bit-rate-capacity of the input portmultiplied by the common-memory period. For example, if the number ofinput ports is 64 and the number of output ports is also 64, and with awrite-access plus read-access interval of each input port of 20nanosecond, the common-memory period is 64×20=1280 nanoseconds. Witheach input port having a capacity of 10 Gb/s, the size of a data blockwould be 12.8 kilobits.

FIG. 1 illustrates a prior-art common-memory switch 100. As describedabove, a common-memory switch relies on massive data parallelism toenable high-speed data storage and retrieval. A switch fabric 150comprises a multiplexer 120, a common-memory assembly 152, and ademultiplexer 140. Common-memory assembly 152 includes a common memory154 and a controller 156. Common memory 154 is shared, in a write-mode,by a plurality of input ports 122 and, in a read mode, by a plurality ofoutput ports 142. Each input port 122 receives data from an incomingchannel 121 and transmits data through a channel 123, multiplexer 120,and channel 124 to the common-memory 154. Each output port 142 receivesdata from common memory 154 through channel 144, demultiplexer 140, andchannel 143 and transmits data through an outgoing channel 141. Theinput ports 122 cyclically access the common memory 154 throughmultiplexer 120 and the common memory 154 is cyclically connected to theoutput ports 142 through demultiplexer 140.

Data is stored in common-memory 154 which comprises parallel memorydevices that are identically addressed. Data blocks 158 are stored incorresponding addresses in the parallel memory devices constituting thecommon memory 154. In a common-memory switch 100, there is no internalcongestion and each stored data block 158 is guaranteed a path to itsdesired output port. Flow-rate regulation may then be applied at eachoutput port of the common-memory switch. Data release from the commonmemory to any output port may be regulated by a flow-rate regulator.

FIG. 2 illustrates time organization into time frames 220 eachcomprising a number S of time slots 222 of Δ seconds duration each. Adata stream having a flow rate of ρ bits per second may be divided intodata segments each containing ρ×Δ bits, or into data blocks eachcontaining S data segments, hence ρ×Δ×S bits. The data received at aninput port of a switching node may be organized in data segments or datablocks each data block having a number of data segments. The receiveddata may also be received in another format then formatted by the inputport into data segments or data blocks. A data block must be switched inits entirety to an output port. A data stream organized in data segmentsmay be assigned designated time slots in a time frame at input andswitched to designated time slots at output. The number of designatedtime slots at output may exceed the number of designated time slots atinput in the case of multicast switching. Traditionally, a data streamassigned designated time slot in a predefined time frame has beenreferenced as a time-division-multiplexed (TDM) data stream. A datastream organized in data segments may also be assigned time slots thatdo not necessarily bear any specific relationship to a time frame or anytime reference. A stream of packets, generally of different sizes andarriving at random, may be segmented into data segments of equal sizeand switched as such within a switching node where, at output, theswitched data segments are reassembled into their original packetformat. The familiar Asynchronous Transfer Mode (ATM) scheme dividespackets of generally variable sizes into data segments called ‘cells’which are switched as such within a switching node. In ATM, however,cells are reassembled into packets at the receiving end and notnecessarily at the output of the switching node that receives theoriginal packets. ATM cells are not required to follow a strict timereference. An ATM switching node, however, may attempt to reduce thecell delay variation to reduce packet-transfer jitter. When a datastream is organized in a TDM format, but with sizeable segments, the TDMformat is referenced as a synchronous transfer mode (STM). Data segmentsthat are aperiodically switched preferably carry identifying headers. Incontrast, data segments that are periodically switched need not carryidentifiers and may be recognized in each switching node they traverseby the time slots they occupy in a recognizable data frame. A switchingnode that switches aperiodic data segments, such as an ATM switchingnode, is by necessity a synchronous switch where data segments arealigned at input. A switching node that switches periodic data segmentsis of course a synchronous switching node but the data frames, not justthe data segments, must be aligned at input. The co-existence ofperiodic and aperiodic data-segment switching is, therefore, feasible ina synchronous switch, such as the rotator-based switch disclosed in U.S.Pat. No. 5,168,492, issued on Dec. 1, 1992 to Beshai et al., and titled“Rotating Access ATM-STM Switch”, and U.S. Pat. No. 5,745,486 issued toBeshai et al. on Apr. 28, 1998 and titled “High Capacity ATM switch”,the specifications of which are incorporated herein by reference. U.S.Pat. No. 5,168,492 also discloses a method of facilitating hybridATM-STM switching where STM switching experiences no delay jitter.

In U.S. Pat. No. 5,168,492, any input port can request periodicswitching, aperiodic switching, or interleaved periodic and aperiodicswitching of its data segments. Data block switching is also possible ineither a periodic or an aperiodic format

Switching entire data blocks, each comprising several data segments, ishighly desirable for data streams of high flow rate. A data stream of 2gigabits per second (Gb/s) accumulates 400 bytes in only 1.6microseconds and the data may therefore be formatted into data blocks of400 bytes for example. The data block may still be partitioned alongsegment lines but all segments of the same data block ought to have thesame destination. Thus, if transferred in a periodic form, the datasegments of a data block would all be identified by a single time slotin a predefined time frame and if transmitted in an aperiodic format, asingle header would be used for the entire data block.

Concurrent-Access Switch

Hereinafter, a switch in which two or more input ports may concurrentlytransmit data to the switch fabric and two or more output ports mayconcurrently receive data through the switch fabric is called a“concurrent-access switch”.

FIG. 3 illustrates a prior-art concurrent-access data switch 300 knownas buffer-space-buffer switch. The switch 300 comprises a switch fabric350, N input ports each having an input buffer 322, and N output portseach having an output buffer 342. Each input port may receive signalsfrom an incoming channel 321 and has a channel 323 to an inlet of switchfabric 350. Each output port may receive signals from an outlet ofswitch fabric 350 through a channel 343 and may transmit signals over anoutgoing channel 341. It is well known that the switching fabric 350 canscale to accommodate a large number of input ports and output ports.However, the use of the switch 300 in a time-shared mode to provide afine granularity requires a contention-resolution mechanism, typicallyimplemented as a scheduler, the complexity of which increases rapidly asthe number of ports increases.

FIG. 4 illustrates the dependence of data-block formation delay on theflow-rate of a data stream in the common-memory switch of FIG. 1(normalized flow rate is used). In a symmetrical common-memory switchhaving N>1 input ports and N output ports, the data-block formationdelay, D, is determine as: D=N×δ×R/ρ, where δ is the common-memoryaccess time (write access plus read access), R is the input-port datarate, and ρ is the flow-rate of the data stream to which the data blockbelongs. As ρ increases, the data-block formation delay decreases asillustrated in FIG. 4 for different values of N. Naturally, thedata-block formation delay increases as N increases. Imposing an upperbound on the formation delay determines a minimum flow rate of a datastream that would be efficiently switched in a common-memory switch. Fora specified value of N, the minimum flow rate ρ* to satisfy a formationdelay tolerance D is then ρ*=N×δ×R/D.

FIG. 5 is derived from FIG. 4 with the values of the normalized flowrate ρ/R ranging from zero to only 0.08. The figure also indicates thepoints corresponding to the value of ρ/R=1/N for a hypotheticalreference case where the data rates from an input port to all outputports of a switch are equal, with the input port receiving data at therated capacity R. For relatively small values of N, the data-blockformation delay may be well below a permissible limit 510 even forvalues of ρ/R smaller than the mean value R/N. For larger values of N,N=256 for example, the data-block formation delay exceeds thepermissible delay 510 even for values of ρ/R that are much larger thanthe mean value R/N.

FIG. 6 illustrates the scalability, in terms of the number of ports of aswitch, as a function of the normalized flow rate ρ/R anddata-block-formation-delay upper bounds in a common-memory switch. Inparticular, the figure illustrates a permissible number of input portsin an exclusive-access (common-memory) switch for different flow ratesand specified data-block formation delay upper bounds. The permissiblenumber of input ports versus the normalized flow rate ρ/R is illustratedfor values of the permissible delay D of 1000δ, 2000δ, 4000δ, and 8000δ(lines 610A, 610B, 610C, and 610D, respectively), where δ is thecommon-memory access time (write plus read). As discussed earlier, in anexclusive-access switch, only one port, input or output, may access acommon memory at any instant of time. For example, if the permissibleformation delay D equals 40006, the permissible number N of input portswould be 160 if the ratio ρ/R is not less than 0.04, but N would bereduced to 80 if the ratio ρ/R is as small as 0.02. This suggests thatdata streams with flow rates below a selected threshold mayadvantageously be diverted to a different switch fabric so that theexclusive-access fabric may be used only for data streams of high flowrates. Switching data streams of flow rates each below the selectedthreshold while observing a formation-delay upper bound would force theformation of incomplete data blocks, each having fewer bits than thecommon-memory width, thus resulting in capacity waste.

FIG. 7 illustrates an exemplary flow-rate distribution in a datanetwork. The figure illustrates the probability of exceeding anormalized flow rate ρ/R of a data stream. The dotted-line 710represents the case where the combined input data at a given input portis divided equally among the output ports, with the number of outputports being equal to the number, N, of input ports. The normalizedflow-rate ρ/R is then equal to 1/N, and the permissible number N isselected so that the data-block formation delay D is below a permissiblelimit. The maximum value of N is then determined as N²≦(D/δ) if thenumber of output ports equals the number of input ports and theread-access time equals the write-access time δ/2. For example, if D=500microseconds, δ=20 nanoseconds, then N should not exceed 158 (theinteger part of the square root of D/δ). The flow rate from an inputport to an output port may vary between 0 and R. The solid line 720represents an exemplary complementary function (i.e., the probability ofexceeding a given normalized flow rate) of the spatial distribution ofthe flow rate among the output ports. In this example, a smallproportion of data streams would have high flow rates, each exceedingthe mean value of R/N. However, the sum of flow rates of the relativelysmall number of data stream, each having a flow rate exceeding the meanvalue R/N, may collectively contribute a high proportion of the totalbit rate.

In the prior-art switch buffer-space-buffer switch, illustrated in FIG.3, data received by each input port is held in an input buffer. When theswitch is operated in a time-sharing mode, which is the case consideredhereinafter, the data is preferably formatted into data segments ofequal size. The input ports may concurrently transfer data across thememoryless space switch to respective output ports. To prevent two ormore input ports from simultaneously transferring data to the sameoutput port, a contention-resolution mechanism may be provided at theswitch. Each input port may continuously transmit data segments tooutput ports and each output port may continuously receive data segmentsfrom input ports according to a schedule determined by a switchcontroller. The size of a data segment is arbitrary. However, when aninput port has data to transmit to numerous output ports, the datasegments are preferably kept reasonably short to reduce delay jitter intransferring the data across the space switch. The size of a typicaldata segment may be less than two kilobits, for example.

As described above, the scalability of the exclusive-access switch isdetermined by the delay tolerance. In a uniform switch structure, forexample, where the input ports have identical capacities, each inputport can access the common-memory during every common-memory period. Fora switch having N input ports and N output ports, with an accessinterval, including write access and read access, of δ seconds, thecommon-memory period is determined as N×δ. The size of a data blockwritten during an access interval is then B=N×δ×R, where R is thecapacity of the input port in bits per second. For example, if N=128,δ=20 nanoseconds, and R is 10 Gb/s, the data block size B isapproximately 25.6 kilobits. The data block formed at an input port maybe destined to one output port. If the flow rate from an input port toan output port is ρ bits per second, then the mean value of the timerequired to form a data block is B/ρ seconds. For example, with ρ=8megabits per second (Mb/s), the ratio B/ρ, which is the mean timerequired to form a data block, is 3.2 milliseconds for B=25.6 kilobits,which may be considered excessive. If ρ=1 Gb/s, the formation delay is25.6 microseconds. In a hypothetical case where the data transmittedfrom an input port is uniformly divided among the output ports, the meantransfer rate from the input port to any output port is R/N, and themean data-block formation time is B/ρ=δ×N². With N=256 and δ=20nanoseconds, the mean data-block formation delay is approximately 1.3milliseconds. With N=64, the data-block formation delay is approximately82 microseconds.

The scalability of the concurrent-access switch structure is determinedprimarily by the speed of the contention-resolution mechanism, i.e., thespeed of the switch scheduler. The scheduling effort is directlyproportional to the total data flow rate across the space switch.

In summary, comparing the exclusive-access switch architecture and theconcurrent-access switch architecture, it is observed that thescalability of the first is governed by the data-block formation delay,which is heavily dependent on the flow rate of each data stream—thehigher the rate, the lower the formation delay—while the scalability ofthe second is determined by the required scheduling effort which isproportional to the total flow rate across the space switch. Notably, asignificant advantage of the exclusive-access architecture is itscontention-free aspect which implies near zero blocking because blockingmay occur only when the entire common memory is fully occupied.

A switch structure, according to the present invention, in which aninput port may choose an exclusive-access mode or a concurrent-accessmode, provides both scalability and high performance.

FIG. 8 illustrates a rotator-based switch, disclosed in theaforementioned U.S. Pat. No. 5,168,492, having input ports 822 andoutput ports 842. During a rotator cycle, an input rotator 820 connectseach input port 822 to each of a plurality of transit memory devices 830in a cyclic manner and output rotator 840 connects each of thetransit-memory devices 830 to each output port 842 in a cyclic manner. Arotator cycle includes a number of time slots equal to the number, J, oftransit-memory devices. During each time slot, an input port maytransmit data to the transit-memory device 830 to which it is connected.Likewise, during a time slot, a transit-memory device transmits data tothe output port 842 to which it is connected. With N>1 denoting thenumber of input ports and M>1 the number of output ports, the number Jof memory devices is at least equal to the larger of N and M, i.e., J≧N,and J≧M. Each of the transit memory devices 830 is logically partitionedinto at least L≧M memory divisions.

The input rotator has N inlets and J outlets, and connects each inputport to each transit-memory device 830 during each rotator cycle where arotator cycle comprises J successive time slots. The output rotator hasJ inlets and M outlets, and connects each transit-memory device 830 toeach output port 842 during each rotator cycle. Each of the N inputports may have an associated input controller (not illustrated) operableto control the transfer of up to J data segments during a rotator cycleto the J transit-memory devices 830.

The combination of input rotator, transit-memory devices, and outputrotator effectively function as a scalable space switch and has severaladvantages over a conventional space switch. The advantages include: (1)structural simplicity, (2) virtually unlimited fabric scalability, and(3) high reliability with ease of recovery from component failure.

FIG. 9 illustrates a switch for handling data streams of disparate flowrates. The switch 900 of FIG. 9 comprises a transit-memory assembly 925,which includes a bank of transit-memory devices 930 interconnecting aninput rotator 920 and an output rotator 940. Input rotator 920 has anumber of inlets equal to the number of input ports 922 and a number ofoutlets equal to the number transit-memory devices 930. Output rotator940 has a number of inlets equal to the number of transit-memory devicesand a number of outlets equal to the number of output ports 942. Theinput rotator 920 and the output rotator 940 have opposite rotationdirections. Each transit-memory device 930 has an associatedtransit-memory controller 932. Input ports 922 receive data fromsubtending data sources (not illustrated in FIG. 9) through an inputchannel 921 and arrange the received data in data segments or largerdata blocks, where a data block contains a number of data segments notexceeding the number of transit memory devices, as will be describedbelow. Each input port 922 has a channel 923 to an inlet of inputrotator 920 and each outlet of input rotator 920 has a channel 924 to atransit memory device 930. Each transit memory device 930 has a channel944 to an inlet port of output rotator 940 and each outlet port ofoutput rotator 940 has a channel 943 to an output port 942. An outputport 942 transmits data read from the transit-memory devices 930 tosubtending data sinks or to another switch (not illustrated in FIG. 9)through a channel 941. Input rotator 920 cyclically connects each inputport to each transit-memory device and output rotator 940 cyclicallyconnects each transit-memory device to each output port. A mastercontroller 960 is communicatively coupled to each input port 922 throughchannels 962 and to each transit-memory controller 932 through a channel964. When a memory division is reserved to hold a data segment, thememory division is marked as occupied and when the data segment istransmitted to an output port, or to multiple output ports in amulticast mode, the memory division is marked as free.

Master controller 960 is operable to determine input-port-specificschedules for data transfer from input ports 922, through input rotator920, to transit memory devices 930, and transit-memory-specificschedules for data transfer from the transit memory devices 930, throughsaid output rotator 940, to output ports 942.

The input rotator 920 may be configured to periodically repeat aninput-configuration cycle having a predefined sequence of input transferconfigurations. Likewise, the output rotator 940 may be configured toperiodically repeat an output-configuration cycle having a predefinedsequence of output transfer configurations. The output transferconfiguration is preferably a mirror image of the input transferconfiguration so that when an input port associated with a specificoutput port connects to a transit-memory device 930, during a time slotin a rotator cycle, the same transit-memory device 930 connects to thespecific output port during the same time slot.

Exclusive-Access Switch

The switch 900 of FIG. 9 can be used as an exclusive-access switch whichfunctions in a manner that is quite similar to that of the wide-memorydescribed with reference to FIG. 1 with the added advantage that inputdata need not be entirely held at the input port until a wide data blockis formed. A rotator-based switch handling data blocks, each traversingan entire set of transit memory devices, is described in Applicant'sU.S. patent application Ser. No. 09/671,140 filed on Sep. 28, 2000 andtitled “multi-grained network”, the specification of which isincorporated herein by reference.

A lateral array is defined hereinafter as an array of transit-memorydivisions that includes one memory division from each of thetransit-memory devices, and as will be described below, mastercontroller 960 of switch 900 of FIG. 9 may schedule as a separate entitya data segment occupying an individual transit-memory division, or adata block occupying an entire lateral array. Each of the N input portstransfers at most a data segment of Ω bits during each of the time slotsof a rotator cycle, and a lateral array contains data segmentsoriginating from a single input port 922 and having at least one commondestination (common output port 942). i.e., a data block is transferredin its entirety to one output port or to multiple output ports 942 in amulticast application. When a lateral array is reserved, it is marked asoccupied and when the lateral array is released it is marked as free.

The master controller 960 may perform processes of: receivingflow-rate-allocation requests from each of the N input ports 922;allocating a permissible transfer rate in response to each of therequests; communicating the permissible transfer rates to correspondinginput ports 922; granting write permits to each of the N input ports,each of the write permits indicating one of the lateral arrays; andgranting permits to transit-memory controllers 932 to transfer datasegments of lateral arrays from transit memory devices 930 to outputports 942 during each rotator cycle. The master controller may alsoinclude a release-rate regulation device operable to select at most oneof the lateral arrays for each of the M output ports during each rotatorcycle. The common memory switch may include an admission-rate regulationdevice associated with the master controller; the admission-rateregulation device would be operable to select at most one of the lateralarrays for each of the N input ports during each rotator cycle. Thecommon-memory switch thus constructed may also include an input rateregulation device associated with each of the N input ports to regulatethe rate of data transfer from each input port to the transit-memorydevices. A data segment may contain information bits and null bits andonly the information bits in each data segment are transmitted from eachof the N output ports.

The input ports 922 and the output ports 942 are paired. In oneembodiment, a paired input port 922 and output port 942 accesses atransit memory 930 during the same time slot. Other disciplines ofaccessing the transit memory devices 930 may be devised. For example,during a rotator cycle, each input port 922 may access each transitmemory device 930 in a write mode during a first part (approximately onehalf) of the rotator cycle then each output port may access each transitmemory device 930 in a read mode during the remaining part of therotator cycle.

Scalability of the Exclusive-Access Switch

The scalability of the rotator-based exclusive-access switch isdetermined primarily by a permissible delay D in forming the consecutivedata segments of a data block—the delay increases with the number oftransit-memory devices. Considering a switch 900 in which the number ofinput ports 922, the number of transit memory devices 930, and thenumber of output ports 942 are equal to a specified number N, the Ninput ports 922 collectively transfer data to the N transit-memorydevices at a rate that is less than the ratio (N×Ω)/Δ so that:

${{\sum\limits_{j = 1}^{N}r_{j}} \geq {\left( {N \times {\Omega/\delta}} \right) \times \left( {1 - {\left( {N - 1} \right) \times N \times {\delta/D}}} \right)}},$

where δ is the time required to access any of the N transit-memorydevices to write and read a data segment, D is a permissible datasegment queueing delay, and r_(j), 1≦j≦N, is the flow rate at which aninput port transfers data to the N transit memory devices.With identical input ports, each of the N input ports 922 transfers datato the set of transit-memory devices 930 at a rate R limited by:

R≦(Ω/δ)×(1−(N−1)×N×δ/D

Where, as above, δ is the time required to access any of the Ntransit-memory devices to write and read a data segment and D is apermissible data segment queueing delay at any of the N input ports.

Optionally, each input port may be allocated at most a first constrainednumber of lateral arrays during a predefined time frame of duration T,the first constrained number being specific to each input port, and eachoutput port may be allocated at most a second constrained number oflateral arrays during the predefined time frame of duration T, thesecond constrained number being specific to the each output port.

Multimodal Switch

Each transit-memory device 930 of switch 900 may be logicallypartitioned into memory divisions and each memory division has thecapacity to hold at least one data segment. The set of transit-memorydevices 930 within transit-memory assembly 925 is logically partitionedinto a first section organized to hold data blocks and a second sectionorganized to hold data segments. Each data block comprises a number ofdata segments not exceeding the number of transit-memory devices in thebank of transit-memory devices 930. The logical structure of thetransit-memory device 930 will be further described with reference toFIGS. 10-14.

In accordance with the present invention, a rotator-based core isstructured to function as a concurrent-access switch and anexclusive-access switch embedded in the same homogeneous structure witharbitrary division of data received from the input ports 922 among thetwo embedded switches. The structure also facilitates the use oftime-division-multiplexing (TDM) switching, as will be described belowwith reference to FIGS. 15-18, and provides a multicasting capabilityfor data blocks in the exclusive-access mode and data segments in theconcurrent-access mode, as will be described below with reference toFIGS. 19-20.

FIG. 10 illustrates the organization of transit memory devices 930 in amultimodal data switch 900 adapted to perform both exclusive-access andconcurrent-access switching in accordance with an embodiment of thepresent invention. In this example, the number of input ports 922, thenumber of transit-memory devices 930, and the number of output ports 942are equal, and the number, N, of input ports is selected to equal four.The number N is selected to equal four to simplify FIG. 10, but it isunderstood that a switch 900 may have any integer number N of inputports or output ports. Each transit-memory 930 is divided into twosections. A first section 1002, used to realize an exclusive-accessswitch, includes an arbitrary number of memory divisions, herein calledprimary memory divisions, each for holding a data segment of a datablock to be transferred from any input port to any output port. A secondsection 1004, used to realize a concurrent-access switch, includes Nmemory divisions, herein called secondary memory divisions, eachdedicated to a corresponding output port. A specific memory divisionassociated with a specific output port may contain a data segmentreceived from any input port but destined to the specific output port.In general, any memory division in any transit memory device 930 may beassociated with a specific output port. However, memory divisions intransit-memory devices 930 used to hold data segments destined to thesame output ports are preferably given identical indices in therespective memory devices 930. Thus, a column (array) 1010 in the firstsection 1002 comprises N primary memory divisions 1012 which may containdata segments written by the same input port and directed to at leastone output port 942 while a column 1020 in the second section 1004 maycontain N secondary memory divisions 1022 which may contain datasegments directed to the same output port but possibly written bydifferent input ports 922. A primary memory division 1012 may beallocated to any input port and any output port and is, therefore,called a ‘floating’ memory division. The data segments held in primarymemory divisions 1012 of a column 1010 form a data block. The secondsection 1004 of a transit-memory 930 is restricted to hold at most onedata segment directed to a specific output port. In contrast, there maybe several data blocks stored in the first section 1002 of thetransit-memory assembly that are destined to the same output port.Hereinafter, the first section 1002 is referenced as an‘exclusive-access section and the second section 1004 is referenced as a‘concurrent-access section’. A data segment may be transferred to aspecific memory division in the concurrent-access section only if thespecific memory division is free, i.e., not reserved to hold a datasegment, while a data block (comprising an array of data segments) maybe transferred to any free address in the exclusive-access section. Itis noted that an address of a data block in section 1002 is reserved ineach transit-memory device 930.

As described earlier, preferably only the information bits of each datasegment are transmitted by an output port, and data transfer from alateral array to an output port is rate regulated according to theinformation-bit content of the lateral array. A method and an apparatusfor efficiently segmenting variable-size packets, in a plurality of datastreams, into segments of equal size is disclosed in Applicant's U.S.patent application titled “Compact segmentation of variable-size-packetsStreams”, filed on Dec. 14, 2000, and assigned Ser. No. 09/735,471, thespecification of which is incorporated herein by reference. The methodconcatenates packets of same destination, but possibly belonging todifferent users, into successive segments in a manner that attempts tominimize segmentation waste while satisfying service-qualityrequirements of each data stream. The method and apparatus may be usedin the multimodal switch 900 of the present invention.

Master controller 960 may receive from input ports 922 flow-rateallocation requests for data streams each defined according to an inputport 922 and an output port 942, amongst other attributes. Given thecapacity of each output port 942, master controller 960 may thendetermine a permissible transfer rate corresponding to eachflow-rate-allocation request and communicate indications of thepermissible rates to respective input ports 922.

In summary, each of the transit-memory devices may be logicallypartitioned into two groups of memory divisions. The first groupincludes an appropriate number of memory divisions and the second groupincludes a number of memory divisions equal to the number of outputports. The appropriate number of memory divisions may be determinedaccording to queueing models well known in the art.

Each memory division in the first group of a particular transit-memorydevice is associated with a ‘peer’ memory division in each othertransit-memory device to form an array that may be assigned to hold adata block. A data block includes a number of data segments, notexceeding the number of transit-memory devices, which are written by asingle input port and destined to at least one output port.

The second group of memory divisions has a one-to-one correspondence tothe output ports 942; each memory division in the second group of memorydivisions of any transit-memory device 930 corresponds to a specificoutput port 942 and may hold a data segment written by any input port922. Thus, the second group of memory divisions has only one memorydivision per output port and all memory divisions of the second group ofdifferent transit-memory devices are independently scheduled.

Selection of Switching Mode

An input port may be adapted to determine a flow rate for each datastream and assign the data stream to the exclusive-access section 1002if the flow rate exceeds a predetermined threshold or to theconcurrent-access section 1004 otherwise. The threshold is governed by aformation-delay tolerance. For a specified value N of a number of inputor output ports, and with a formation-delay tolerance τ substantiallyexceeding the duration of a rotator cycle, the minimum flow rate ρ* tosatisfy the formation delay tolerance τ is then ρ*=N×δ×R/τ, as describedearlier with reference to FIG. 4. R is the input-port maximum flow rateand δ is the access time (write access plus read access) of a transitmemory 930.

An input port may also determine an estimate of data volume directed toa specific output port and select the exclusive-access section or theconcurrent-access section according to the estimated data volume. Theselection of either section may also be influenced by a permissibledelay. An input port may determine a delay tolerance for each datastream and assign each data stream to one of the two sectionsaccordingly. Regardless of the selection criterion, an identifier of theselected section (1002 or 1004) is communicated to the master controller960 for scheduling purposes.

A person skilled in the art will realize that the transit-memoryassembly 925 may include the first section 1002, the second section1004, or both sections. Thus switch 900 may be operated as anexclusive-access switch, a concurrent-access switch, or both.

An input port 922 may receive data of different types, such as periodicdata segments, or aperiodic data packets to be divided into datasegments of equal size to facilitate internal switching. The input portmay classify the received data according to predefined criteria andcommunicate the classification to the master controller 960 forscheduling purposes.

Transit-Memory Organization

FIG. 11 illustrates the exclusive-access section of a switch 1100(similar to switch 900 of FIG. 9) with a transit assembly 1125comprising transit memory devices 1130 interpose an input rotator 1120receiving from input ports 1122 and an output rotator 1140 transmittingto output ports 1142. Data blocks may be organized in the transit memoryassembly 1125 as an interleaved linked list with spatial alignment ofthe data blocks. The data segments of the data blocks are spatiallyaligned, where each input port 1122 starts to write a data blockcomprising N data segments at a predefined reference transit memory;1130-0 for example, N being the number of transit-memory devices 1130 inthe transit-memory assembly 1125 (in the example of FIG. 11, N is thenumber of input ports or output ports). Thus, the starting segment ofthe data block written by any input port appears in the referencetransit memory. The reference transit memory is preferably transitmemory 1130-0. The memory divisions in the concurrent-access sectionhave a one-to-one correspondence to the output ports and are notillustrated in FIG. 11.

The exemplary switch fabric 1100 has four input ports 1122 labeled A, B,C, and D, four transit-memory devices 1130, and four output ports 1142labeled A*, B*, C*, and D*. Each of the four transit-memory devices 1130is organized into twelve memory divisions. Twelve arrays 1110 of memorydivisions, each array 1110 having one memory division from each of thefour transit-memory devices, serve to hold at most twelve data blocks,each data block having four data segments. An incomplete data block,having less than four data segments, may be complemented by null data.The memory divisions in each array are preferably likewise addressed intheir respective transit-memory devices 1130. In the example illustratedin FIG. 11, seven of the twelve arrays 1110 hold data blocks and theremaining five arrays are free (not currently reserved). Three arrays,each labeled {A0, A1, A2, A3}, correspond to data blocks each havingfour data segments written by input-port A. Three arrays, each labeled{B0, B1, B2, B3} correspond to data blocks each having four datasegments written by input port B. One array labeled {C0, C1, C2, C3} hasfour data segments written by input port C, and one array labeled {D0,D1, D2, D3} has four data segments written by input port D. A mastercontroller (similar to master controller 960 of FIG. 9, not illustratedin FIG. 11) forms four interleaved linked lists 1152 within an array1150, each linked list corresponding to data blocks destined to one ofthe output ports A*, B*, C*, and D*. A linked list, in the interleavedlinked lists, corresponding to a specific output port may be empty ifthe bank of transit-memory devices 1130 does not hold any data blocksdestined to the specific output port. Data blocks may occupynon-consecutive addresses in the bank of transit memories because theinter-arrival times of data blocks of a data stream may not be equal (asmentioned earlier, a data stream is defined by an input port and anoutput port, amongst other attributes). Therefore, data blocks are notnecessarily released in the same order in which they are received.

FIG. 12 illustrates the operation of a switch 1200, similar to switch900 of FIG. 9, as an exclusive-access switch 1200 with data blocksorganized in the memory devices as an interleaved linked list withtemporal alignment of the data blocks. A transit assembly 1225comprising transit memory devices 1230 interpose an input rotator 1220and an output rotator 1240. Temporal alignment means that a first datasegment of a data block is transferred to a transit memory device duringa reference time-slot of a rotator cycle. The reference time slot ispreferably the first time slot in a rotator cycle. Each input port maystart to write a data block comprising N data segments at time-slot 0 ofthe rotator cycle. Thus, the starting segment of the data block writtenby a specific input port appears in the transit memory device to whichthe input port is connected at time-slot 0. In FIG. 12, two data blockswritten by input-port ‘A’ start at transit-memory 1230-0 and one datablock written by input port ‘D’ starts at transit-memory 1230-3.

It is noted that, with temporal data-block alignment, the first-writtendata segment of a data block is not necessarily the first-read datasegment of the data block. Therefore, a data block received at a givenoutput port may be rearranged to place the first-written data segment inthe front of a rearranged data block. The rearrangement is deterministicand is determined by relative positions of the input and output portsspecified in a connection. With spatial data-block alignment, thefirst-written data segment of a data block is also the first-read datasegment of the data block and no rearrangement is required.

The exemplary switch 1200 has four input ports labeled A, B, C, and D,four transit-memory devices 1230, and four output ports labeled A*, B*,C*, and D*. As in the case of switch 1100, each of the fourtransit-memory devices 1230 is organized into twelve memory divisions.Twelve lateral arrays of memory divisions, each lateral array having onememory division from each of the transit-memory devices, serve to holdat most twelve data block, each data block having at most four datasegments. An incomplete data block, having less than four data segments,may be complemented by null data. The memory divisions in each array arepreferably likewise addressed in their respective transit-memorydevices. In the example illustrated in FIG. 12, seven of the twelvearrays hold data blocks and the remaining five arrays are free. Threearrays, each labeled {A0, A1, A2, A3}, correspond to data blocks eachhaving four data segments written by input port A. Three arrays, eachlabeled {B3, B0, B1, B2} correspond to data blocks each having four datasegments written by input port B. One array labeled {C2, C3, C4, C0} hasfour data segments written by input port C, and one array labeled {D1,D2, D3, D0} has four data segments written by input port D. A mastercontroller (not illustrated in FIG. 12, similar to master controller 960of FIG. 9) forms four interleaved linked lists 1252 within an array1250, each linked list corresponding to data blocks destined to one ofthe output ports A*, B*, C*, and D*.

Spatial Versus Temporal Alignment of Data Blocks

FIG. 13 illustrates the data organization in the transit memory devicesin a combined exclusive-access and concurrent-access switch 1300(similar to switch 900 of FIG. 9) having eight transit-memory devices1330 interposing an input rotator 1320 and an output rotator 1340. Datablocks are spatially aligned where the first data segment of each datablock comprising eight data segments is written in the top transitmemory device 1330-0. There are twelve arrays of memory divisions in theexclusive-access section 1302 of the transit-memory assembly and eightarrays of memory divisions in the concurrent-access section 1304 of thetransit-memory assembly; each array includes one memory division in eachof the transit memories. In the exclusive-access section 1302, there isone array {C0, C1, . . . , C7} written by input C and destined to outputH*, two arrays {E0, E1, . . . , E7} written by input port E; onedestined to output B* and the other to output H*, etc., as indicated bycorresponding entries 1338 in array 1380. The interleaved linked list inarray 1380 is managed by a master controller (not illustrated in FIG.13, corresponding to master control 960 of FIG. 9). Theconcurrent-access section 1304 has data segments destined to outputs A*,C*, D*, E*, F*, and G*, as indicated by entries 1334 in array 1380, butno data segments destined to B* or H* because the scheduler reserved thetwo output ports B* and H* to temporarily receive data blocks from theexclusive-access section of the transit-memory assembly comprising theeight transit-memory devices 1330. As indicated, the memory divisions ofan array in the concurrent-access division corresponding to an outputport may contain data segments written by different input ports.

FIG. 14 illustrates the data organization with temporal alignment ofdata blocks in the transit memory devices 1430 of a combinedexclusive-access and concurrent-access switch 1400 (similar to switch900 of FIG. 9) having eight transit-memory devices 1430 interposing aninput rotator 1420 and an output rotator 1440. With temporal alignment,the transit-memory device 1430 holding the first data segment of eachdata block varies according to the input port that writes the datablock. There are twelve arrays of memory divisions in theexclusive-access section 1402 of the transit-memory assembly and eightarrays of memory divisions in the concurrent-access section of thetransit-memory assembly; each array includes one memory division in eachof the transit memory devices 1430. In the exclusive-access section,there is one array {C0, C1, . . . , C7} written by input C and destinedto output H*, as indicated by corresponding entry 1338 in array 1480.The first data segment C0 of the array is written in transit memory1430-2 and the last data segment C7 is written in transit memory device1430-1. (In the spatial alignment scheme of FIG. 13, C0 would be writtenin transit-memory device 1430-0 and C7 would be written intransit-memory device 1430-7). Two arrays {E0, E1, . . . , E7} arewritten by input port E one destined to output B* and the other tooutput H* as indicated by corresponding entries in array 1480, and thefirst data segment of each of the two arrays is written in transitmemory device 1430-4. The interleaved linked list in array 1480 ismanaged by a master controller (not illustrated in FIG. 14—similar tocontroller 960 of FIG. 9). The concurrent-access section 1404 has datasegments destined to outputs A*, C*, D*, E*, F*, and G*, as indicated byentries 1434 of array 1480, and has the same organization of theconcurrent section 1304 of FIG. 13.

TDM Switching

FIG. 15 illustrates a switch 1500, similar to switch 900 of FIG. 9 andadapted to function as a TDM switch with an arbitrary number of datasegments per TDM time frame. FIG. 15 comprises transit-memory devices1530 interposing an input rotator 1520 and an output rotator 1540. Eachtransit-memory device 1530 is organized into an exclusive-access sectionand a concurrent-access section 1504 as in switch configurations 900,1100, 1200, 1300, and 1400. Only the concurrent-access section 1504 isillustrated in FIG. 15. The concurrent-access memory divisions of eachtransit-memory device 1530 may be scheduled for TDM switching or formixed TDM and packet switching. The exemplary switch 1500 has five inputports 1522A, 1522B, 1522C, 1522D, and 1522E, for brevity referenced asA, B, C, D, and E, respectively, and five output ports 1542A*, 1542B*,1542C*, 1542D*, and 1542E*, for brevity referenced as A*, B*, C*, D*,and E*, respectively. Input rotator 1520 cyclically connects the inputports 1522 to the transit-memory devices 1530 of transit-memory assembly1525 and output rotator 1540 cyclically connects the transit-memorydevices 1530 to the output ports 1542. Each input port assembles datainto a TDM frame having an arbitrary number ν of time slots numbered 0to (ν−1). The input ports 1522 transmit data to the output ports 1542through input rotator 1520, the transit-memory assembly 1525 comprisingfive transit memory devices 1530, and output rotator 1540. Eachconcurrent-access section of transit-memory device 1530 is logicallydivided into five memory divisions 1532 each corresponding to an outputport 1542.

In switch 1500, the number of time slots per TDM frame need not be equalto, or bear any rational relationship to, the number of time slots in arotator cycle which equals the number of transit memory devices 1530. Aswill be illustrated below, the TDM frame may include an arbitrary numberof time slots. If the number of time slots per TDM frame is not equal tothe number of time slots per rotator cycle (which, in turn, equals thenumber of transit-memory devices 1530), data segments occupyinglikewise-numbered time slots in successive TDM frames may be written indifferent transit memory devices. For example, with a TDM frame of 8time slots (ν=8), data segments a0, a1, a2, a3, and a4 transmitted byinput port 1522A during a first time slot of each of five successive TDMframes are written in transit memory devices 1520-0, 1530-3, 1530-1,1530-4, and 1530-2, respectively, as indicated in FIG. 15. If the numberof time slots per TDM frame exceeds the number of transit-memory devices1530, an input port may access a given transit memory device 1530,through the input rotator, more than once during a TDM frame. As will bedescribed below, the mapping of an input time slot of a TDM frame ontodifferent transit memory devices does not affect the transit delay,which is the waiting time of a data segment in a transit memory device1530. FIG. 15 illustrates the case of five input or output ports.Different numbers of input/output ports will be used in FIGS. 14-16 toillustrate the flexibility of TDM switching in switch 1500. A mastercontroller (not illustrated) similar to master controller 960 of FIG. 9is included in switch 1500.

FIG. 16 illustrates the transit-memory access pattern in the switch ofFIG. 15 where the number of time slots per TDM frame is smaller than thenumber of transit-memory devices 1530. Table 1600 illustrates theconnectivity pattern during successive TDM frames. The table relates toswitch 1500 having a number ν of time slots per TDM frame equal to 4.The header in Table 1600 refers to input ports 1522-x and output ports1542-x, x=0, 1, 2, 3, and 4. During each time slot, an input port 1522-xaccesses a transit-memory device 1530-y in a write-mode and an outputport 1542-x, associated with input port 1522-x, accesses the sametransit-memory device 1530-y in a read mode. Other access disciplinesmay be devised. Each column (array) 1628 corresponds to an input port1522-x or an output port 1542-x and each entry in the column contains atime-slot identifier 1612 (0 to 3) and a transit-memory identifier 1614(between parentheses and labeled as 0 to 4 in this example) to whichinput port 1522-x and output port 1542-x connect during each ofsuccessive time slots. In the example of FIG. 16, input port 1522-0 andoutput port 1542-0 access transit-memory devices 1530-0, 1530-1, 1530-2,and 1530-3 during a first TDM frame, then access transit-memory devices1530-4, 1530-0, 1530-1, and 1530-3 during the subsequent TDM frame.Likewise, input port 1522-2 connects to transit-memory devices 1530-2,1530-3, 1530-4, and 15340-0 during the first TDM frame and connects totransit-memory devices 1530-1, 1530-2, 1530-3, and 1530-4 during thesubsequent TDM frame.

It is observed from FIG. 16 that the connectivity pattern shifts duringsuccessive TDM frames. Because the number of time slots per TDM frame isnot equal to the number of transit-memory devices, the connectivitypattern varies in successive TDM frames. However, the connectivitypattern repeats every Q time slots, where Q is an integer multiple ofboth the number of transit-memory devices and the number of time slotsper TDM frame. In the example of FIG. 16, Q=20 time slots.

In the example of FIG. 16, each of input ports 1522-0, 1522-1, 1522-3,and 1522-4 has one time-slot per TDM frame allocated for transmission tooutput port 1542-2. The time slots of a TDM frame are indexed as 0, 1,2, and 3. One of many connectivity patterns is indicated below.Coincidentally, each of the four input ports 1522 transmitting to outputport 1542-2 has reserved time slot 1 of the TDM frame. Of course,different input time slots may have been used. For example, the fourinput ports 1522-0, 1522-1, 1522-3, and 1522-4 could have reserved timeslots 2, 0, 0, and 2 respectively. The scheduling of time slots may beperformed by the master controller of switch 1500 or throughcommunications between the input ports 1522 and controllers (notillustrated—similar to controllers 932 of FIG. 9) of the transit-memorydevices 1530.

Input port 1522-0 (column x=0) reserves time-slot 1 of each TDM frame towrite data segments directed to output port 1542-2 during successive TDMframes. The data segments are written in transit-memory devices 1530-1,1530-0, 1530-4, 1530-3, 1530-2, 1530-1, and so on.

Input port 1522-1 (column x=1) reserves time-slot 1 of each TDM frame towrite data segments directed to output port 1542-2. The data segmentsare written in transit-memory devices 1530-2, 1530-1, 1530-0, 1530-4,1530-3, 1530-2, and so on, as illustrated by parallel arrows 1640-1.

Input port 1522-3 (column x=3) reserves time-slot 1 of each TDM frame towrite data segments directed to output port 1542-2. The data segmentsare written in transit-memory devices 1530-4, 1530-3, 1530-2, 1530-1,1530-0, 1530-4, and so on, as illustrated by parallel arrows 1640-3.

Input port 1522-4 (column x=4) reserves time-slot 1 of each TDM frame towrite data segments directed to output port 1542-2. The data segmentsare written in transit-memory devices 1530-0, 1530-4, 1530-3, 1530-2,1530-1, 1530-0, and so on, as illustrated by parallel arrows 1640-4.

FIG. 17 illustrates the transit-memory access pattern in the switch ofFIG. 15 where the number ν of time slots per TDM frame is equal to thenumber J of transit-memory devices 1530 (ν=J=5). In the example of FIG.17, each of input ports 1522-0, 1522-1, and 1522-3 has one time-slot perTDM frame allocated for transmission to output port 1542-2 and inputport 1522-4 has two time slots per TDM frame allocated for transmissionto output port 1522-2. One of many connectivity patterns is indicated inTable 1700. The header in Table 1700 refers to input ports 1522-x andoutput ports 1542-x, x=0, 1, 2, 3, and 4.

Input port 1522-0 (column x=0) reserves time-slot 0 of each TDM frame towrite data segments directed to output port 1542-2, and the datasegments are written in the same transit-memory device 1530-0 duringsuccessive TDM frames.

Input port 1522-1 (column x=1) reserves time-slot 1 of each TDM frame towrite data segments directed to output port 1542-2 and the data segmentsare written in the same transit-memory device 1530-2 during successiveTDM frames.

Input port 1522-3 (column x=3) reserves time-slot 3 of each TDM frame towrite data segments directed to output port 1542-2, and the datasegments are written in the same transit-memory device 1530-1 duringsuccessive TDM frames.

Input port 1522-4 (column x=4) reserves time-slots 0 and 4 of each TDMframe to write data segments directed to output port 1542-2, and thedata segments are written in the same transit-memory devices 1530-4 and1530-1 during successive TDM frames.

Thus, during each TDM frame, output port 1542-2 receives, through thetransit-memory assembly, one data segment from each of input ports1522-0, 1522-1, and 1522-3, and two data segments from input port1522-4. In this example, the connectivity patterns are identical insuccessive TDM frames because the number ν of time slots per TDM frameequals the number J of transit-memory devices 1530. As illustrated,during each time-slot 0 of a TDM frame, output port 1542-2 reads a datasegment from transit-memory 2 written by input port 1522-1. Duringtime-slots 1, 2, 3, and 4, output port 1542-2 reads data segments fromtransit memories 3, 4, 0, and 1, written by input ports 1522-4, 1522-4,1522-0 and 1522-3, respectively, as indicated by lines 1740.

FIG. 18 illustrates the transit-memory access pattern in the switch ofFIG. 15 where the number ν of time slots per TDM frame is larger thanthe number J of transit-memory devices 1530. In this e×ample, there arefive transit-memory devices (1330-0 to 1530-4) and the TDM framecontains eight time slots (ν=8, J=5). In the example of FIG. 18, seventime slots per TDM frame are scheduled. The numbers of time slots perTDM frame allocated to input ports 1522-0, 1522-1, 1522-3, and 1522-4for transmission to output port 1542-2 are 3, 1, 1, and 2, respectively.One of many connectivity patterns is indicated in Table 1800. The headerin Table 1800 refers to input ports 1522-x and output ports 1542-x, x=0,1, 2, 3, and 4.

Input port 1522-0 (column x=0) reserves time-slots 0, 2, and 4 of eachTDM frame to write data segments directed to output port 1542-2. Duringa first TDM frame, the data segments are written in transit-memorydevices 1530-0, 1530-2, and 1530-4. During the second TDM frame, thedata segments are written in transit memory devices 1530-3, 1530-0, and1530-2 and during the third TDM frame, the data segments are written intransit memory devices 1530-1, 1530-3, 1530-0, and so on.

Input port 1522-1 (column x=1) reserves time-slot 0 of each TDM frame towrite data segments of a stream directed to output port 1542-2. The datasegments of the stream are written in transit-memory devices 1530-1,1530-4, 1530-2, 1530-0, 1530-3, 1530-1, and so on.

Input port 1522-3 (column x=3) reserves time-slot 0 of each TDM frame towrite data segments of a stream directed to output port 1542-2. The datasegments of the stream are written in transit-memory devices 1530-3,1530-1, 1530-4, 1530-2, 1530-0, 1530-3, and so on.

Input port 1522-4 (column x=4) reserves time-slots 0 and 6 of each TDMframe to write data segments directed to output port 1542-2. During thefirst TDM frame, the data segments are written in transit-memory devices1530-4 and 1530-0. During the second TDM frame, the data segments arewritten in transit memory devices 1530-2 and 1530-3 and during the thirdTDM frame, the data segments are written in transit memory devices1530-0 and 1530-1.

Thus, during each TDM frame, output port 1542-2 receives, through thetransit-memory assembly 1525, three data segment from input port 1522-0,one data segment from input port 1522-1, two data segments from inputport 1522-3, and two data segments from input port 1522-3. Theconnectivity pattern varies in successive TDM frames but, as describedwith reference to FIG. 16, the connectivity pattern repeats insuccessive periods of Q time slots each, where Q is an integer multipleof both the number of transit-memory devices and the number of timeslots per TDM frame. In this example, Q=40 time slots.

As illustrated, during the second TDM frame, output port 1542-2 reads adata segment from transit-memory 0 written by input port 1522-4. Duringtime-slots 2 to 7, output port 1542-2 reads data segments from transitmemory devices 1530-2, 1530-3, 1530-4, 1530-0, 1530-1, and 1530-2,written by input ports 1522-4, 1522-0 and 1522-1, 1522-0, 1522-3, and1522-0 respectively, as indicated by lines 1840.

It is noted that the transit delay of a data segment written by an inputport 1522-x to be read by an output port 1542-y, 0≦x<N, 0≦q<N, isdetermined as [N+x−y] modulo N and is independent of the number ν oftime slots per TDM frame, as observed in FIGS. 16, 17, and 18.

Multi-Casting

FIG. 19 illustrates data structures 1900 used to facilitateexclusive-access multicasting in the multimodal data switch of FIG. 9.Data blocks are held in a data memory 1910, which represents theexclusive-access section 1002 (FIG. 10) of the set of transit-memorydevices 930 of transit-memory assembly 925 of switch 900. A memory block1912 in the data memory 1910 corresponds to an array (column) 1010 (FIG.10) in transit-memory assembly 925 (FIG. 9). The data structure used tomanage the storage and removal of data blocks from memory blocks 1912 inthe data memory 1910 comprises: an array 1920 containing pointers 1922to successive data blocks in data memory 1910 belonging to the same datastream; an array 1930 containing an indicator 1932 of the number ofdestinations (output ports) of each data block 1912 in data memory 1910;a memory-address dispenser array 1940 containing a list of freeaddresses in data memory 1910; an array 1950 of pointers to thedata-memory address of the head data unit of each data stream; and anarray 1960 of pointers to the address of the end data unit of each datastream. Each array in the data structure 1900 may be updated with eachaddition or removal of a data block. The number of entries in each ofdata memories 1910, 1920, 1930, and 1940 equals the number of arrays(columns) 1010 (FIG. 10) in transit-memory assembly 925. The number ofentries in each of arrays 1950 and 1960 equals the permissible maximumnumber of data streams. Each entry in memory-address-dispenser array1940 includes an address of a free (i.e., unassigned) array 1010 (FIG.10) in the transit-memory assembly 925 (FIG. 9). Array 1940 isinitialized by the addresses of each array 1010 in the transit-memoryassembly 925. The initial addresses may be placed in array 1940 in anarbitrary order; for example a sequential order. With identicaltransit-memory devices 930 (FIG. 9), an address of an array 1010 is theaddress of any of its constituent primary memory divisions 1012 (FIG.10).

FIG. 20 illustrates a data structure 2000 used by master controller 960to facilitate concurrent-access multicasting in a multimodal data switch900 (FIG. 9) for the special case where the number of time slots pertime frame equals the number of transit-memory devices 930. The numberof output ports equals the number N of input ports in this example. Afirst matrix 2020 has N columns, each corresponding to an input port,and N rows, each corresponding to a transit-memory device 930. A secondmatrix 2030 also has N columns each corresponding to an output port andN rows, each corresponding to a transit-memory device. Each entry 2022in matrix 2020 contains a corresponding occupancy state (free/busyrepresented by a single bit for example—not illustrated in FIG. 20) andeach entry 2032 in matrix 2030 contains a corresponding occupancy state2031. For illustration only, a cyclic time slot 2022 of a rotator cycleat which an input port connects to a transit memory is indicated inmatrix 2020 and a cyclic time slot 2032 at which a transit memoryconnects to an output port is indicated in matrix 2030. The cyclic timeslots 2022 and 2032 may be used to determine transit delays but may notbe needed for scheduling purposes.

To schedule the transfer of a data segment from a specific input port toa list of q target output ports, 1≦q<N, a row in matrix 2030,corresponding to a candidate transit-memory, is selected and the entriescorresponding to the output ports in the list of q target output portsare examined. If the entry corresponding to the specific input port andthe candidate transit memory is busy, another candidate transit memorymay be selected. Otherwise, the occupancy states corresponding to thecandidate transit memory and output ports included in the list of qtarget output ports are examined to identify target output ports thatcan be connected through the candidate transit memory and the number ofavailable connections is recorded. The process may be repeated usingother candidate transit memories and the transit memory yielding thehighest connections is selected. If the number of highest connections islower than the specified number q, the remaining connections may beestablished through another transit memory. With partial success, i.e.,if less than q connections can be established, a multicast connectionrequest may be accepted or rejected depending on the admission policy.Naturally, only the selected entries in matrix 2020 and matrix 2030 aremarked busy and when a connection is terminated the correspondingentries in matrices 2020 and 2030 are marked free.

In general, to schedule the transfer of data segments from input portsto output ports through a number of data memories, where the datamemories have cyclic access to the input ports and output ports duringsuccessive time slots of a time-slotted frame, an association of eachinput port with the data memories during successive time slots, i.e., atime-space map, is first determined. A first matrix having a number ofrows equal to the number of data memories and a number of columns equalto the number of input ports is then created. Each entry in the firstmatrix indicates a corresponding input-port occupancy state. A secondmatrix having a number of rows equal to the number of data memories anda number of columns equal to the number of output ports is also created.Each entry in the second matrix indicates a corresponding output-portoccupancy state.

Upon receiving a request to transfer a specified number of data segmentsfrom a specified input port to a specified output port within thetime-slotted frame, a vacancy-matching process is carried out whichincludes steps of selecting a candidate data memory, reading a firstoccupancy state from an entry in the first matrix corresponding to thecandidate data memory and the specified input port, and, if the firstoccupancy state is favorable (indicating availability), reading a secondoccupancy state from an entry in the second matrix corresponding to thecandidate data memory and the specified output port. If the secondoccupancy state is favorable, the number of allocable time slots(initialized as zero) is increased by one. The process is repeated untila sufficient number of time slots is allocated or all data memories havebeen considered.

Thus, the invention provides a multi-modal switch that is flexiblypartitioned into an exclusive-access common-memory-like section and aconcurrent-access space-switch-like section and which enables efficientswitching of data stream of disparate flow rates.

In view of the description above, it will be understood by those ofordinary skill in the art that modifications and variations of thedescribed and illustrated embodiments may be made within the scope ofthe inventive concepts. Moreover, while the invention is described inconnection with various illustrative structures, those of ordinary skillin the art will recognize that the invention may be employed with otherstructures. Accordingly, the invention should not be viewed as limitedexcept by the scope and spirit of the appended claims.

1. A switch comprising: a plurality of input ports; a plurality ofoutput ports; and a plurality of transit-memory devices each cyclicallyconnecting to each of said input ports and output ports during apredefined time-slotted frame, and each logically partitioned into afirst group of primary memory divisions each for holding a data segmentfrom any of said input ports destined to any of said output ports; and asecond group of secondary memory divisions having a one-to-onecorrespondence to said output ports.
 2. The switch of claim 1 whereinsaid primary memory divisions are arranged into memory blocks eachmemory block including one primary memory division from eachtransit-memory device.
 3. The switch of claim 2 wherein each of saidmemory blocks is allocable to hold a data block written by a singleinput port and destined to at least one output port.
 4. The switch ofclaim 1 further comprising: a plurality of transit-memory controllerseach transit-memory controller associated with each of saidtransit-memory devices; and a master controller communicatively coupledto each of said input ports and each of said transit-memory controllers.5. The switch of claim 4 wherein said master controller is operable to:receive, from said input ports, scheduling requests each schedulingrequest associated with a specific data segment from a specific inputport and including an identifier of a specific data stream to which saidspecific data segment belongs; determine a preferred group, from saidfirst group and said second group, to receive said specific datasegment; determine a transfer time of said specific data segment fromsaid specific input port to said preferred group; communicate saidtransfer time to respective input ports; determine an address in each ofsaid transit memory devices from which address a data segment is to betransferred to an output port during each time slot in said time-slottedframe; and communicate said address to said each of said transit memorydevices.
 6. The switch of claim 4 wherein each of said input ports isadapted to determine a flow rate ρ for each data stream from a pluralityof data streams, assign said each data stream to a preferred group fromsaid first group and said second group according to said flow rate, andcommunicate an identifier of said preferred group to said mastercontroller.
 7. The switch of claim 4 wherein each of said input ports isadapted to determine a delay tolerance τ for each data stream from aplurality of data streams and assign said each data stream to said firstgroup if said delay tolerance exceeds a predetermined threshold.
 8. Theswitch of claim 6 wherein said at least one input port selects saidfirst group when the flow rate ρ exceeds a predetermined flow-ratethreshold ρ*.
 9. The switch of claim 8 wherein said flow-rate thresholdis determined as:ρ*=N×R×δ/d, where N is the number of input ports in said plurality ofinput ports, R is a flow rate limit of each of said input ports, δ isthe access time of each of said transit-memory devices, and d is a delaytolerance of said each data stream.
 10. The switch of claim 3 whereindata segments in said data block are transferred from said single inputport to said plurality of transit memory devices in temporal alignment,where said single input port transfers a first data segment of said datablock at a reference time-slot of said time-slotted frame.
 11. Theswitch of claim 3 wherein data segments in said data block aretransferred from said single input port to said plurality of transitmemory devices in spatial alignment, where said single input porttransfers a first data segment of said data block to a referencetransit-memory device.
 12. A switch comprising: a plurality of inputports for receiving input data and organizing said input data into datasegments; a plurality of output ports; a plurality of transit memorydevices; a plurality of transit-memory controllers, each transit-memorycontroller associated with a specific transit memory device; an inputrotator operable to cyclically connect each input port to each transitmemory device; an output rotator operable to cyclically connect eachtransit memory device to each output port; and a master controllercommunicatively coupled to each of said input ports and each of saidtransit-memory controllers.
 13. The switch of claim 12 wherein eachtransit-memory controller is operable to allocate a dedicated memorydivision in said specific transit memory device to each output port forreceiving from any input port a data segment destined to said eachoutput port, thereby realizing concurrent-access switching.
 14. Theswitch of claim 12 wherein each transit-memory controller is furtheroperable to reserve a prescribed number of floating memory divisions insaid specific transit memory device, each floating memory division forreceiving from any input port a data segment destined to at least oneoutput port.
 15. The switch of claim 14 wherein said master controlleris operable to allocate at least one array of floating data divisions,each array including one floating memory division from each transitmemory device, for transferring a data block from a selected input portto at least one output port, said data block including a number of datasegments not exceeding the number of said transit memory devices,thereby realizing exclusive-access switching.
 16. The switch of claim 15wherein said master controller is further operable to determine:input-port-specific schedules for data transfer from said input ports,through said input rotator, to said transit memory devices; andtransit-memory-specific schedules for data transfer from said transitmemory devices, through said output rotator, to said plurality of outputports.
 17. The switch of claim 16 wherein said master controller isfurther operable to communicate said input-port-specific schedules tocorresponding input ports and said transit-memory-specific schedules tocorresponding memory controllers.
 18. The switch of claim 12 whereineach input port further identifies each data segment according to a datatype and communicates an identifier of said each data type to the mastercontroller.
 19. The switch of claim 18 wherein said data type is one of:aperiodic data segments, periodic data segments, and data blocks each ofwhich data blocks comprising a data segment in each of said transitmemory devices
 20. The switch of claim 12 wherein said master controlleris further operable to: receive from at least one of the input portsflow-rate-allocation requests for data-streams, each data streamassociated with an output port; determine a permissible transfer rate inresponse to each of said flow-rate-allocation requests based on a knowncapacity of each output port; and communicate said permissible transferrate to said each of said at least one of the input ports.
 21. Theswitch of claim 12 wherein said input rotator periodically repeats aninput-configuration cycle, said input configuration cycle comprising apredefined sequence of input transfer configurations.
 22. The switch ofclaim 12 wherein said output rotator periodically repeats anoutput-configuration cycle, said output-configuration cycle comprising apredefined sequence of output transfer configurations.
 23. The switch ofclaim 12 wherein each of said transit memory devices is organized tohold data segments directed to a multiplicity of output ports, said datasegments having the same size.
 24. The switch of claim 23 wherein eachtransit-memory controller arranges pointers to data segments held in itsassociated transit memory device so that pointers of data segmentsdirected to the same output port form a linked list
 25. The switch ofclaim 15 wherein said master controller further includes a release-rateregulation device operable to select one of said data blocks for each ofthe output ports during each rotator cycle.
 26. The switch of claim 15wherein at least one of said data blocks contains information bits andnull bits and only the information bits in each data block aretransmitted from each of the output ports.
 27. The switch of claim 15wherein each of said input ports transfers data at a rate R limited to:R≦(Ω/δ)×(1−N×(N−1)×δ/D) where δ is the time required to access any ofsaid transit memory devices to write and read a data segment, Ω is thenumber of bits per data segment, D is a permissible data segmentqueueing delay at any of the input ports, and N is the number of inputports.
 28. The switch of claim 15 wherein data-block transfer to anoutput port is rate regulated according to the information-bit contentof said data block.
 29. The switch of claim 15 wherein at least one ofsaid transit-memory controllers is further adapted to provide multiplepointers for a single data segment held in a transit memory device. 30.The switch of claim 29 wherein each of said single data segments isdeleted when addressed by all of the multiple pointers.